Conductive images on non-conductive or dielectric surfaces are ubiquitous in today's technology-driven world. Perhaps the most widely known example of such are the integrated circuits found in virtually all electronic devices. Integrated circuits result from a sequence of photographic and chemical processing steps by which the circuits are gradually created on a dielectric substrate such as a silicon wafer.
A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots, called boules, that are up to 300 mm in diameter. The boules are then sliced into wafers about 0.75 mm thick and polished to obtain a very smooth flat surface.
The formation of a circuit on a wafer requires numerous steps that can be categorized into two major parts: front-end-of-line (FEOL) processing and back-end-of-line (BEOL) processing.
FEOL processing refers to the formation of circuits directly in the silicon. The raw wafer is first subjected to epitaxy, the growth of crystals of ultrapure silicon on the wafer wherein the crystals mimic the orientation of the substrate.
After epitaxy, front-end surface engineering generally consists of the steps of growth of the gate dielectric, traditionally silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In dynamic random access memory (DRAM) devices, storage capacitors are also fabricated at this time, typically stacked above the access transistor.
Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits, which comprise the BEOL portion of the process. BEOL involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material was traditionally a form of silicate glass, SiO2, but other low dielectric constant materials can be used.
The metal interconnecting wires often comprise aluminum. In an approach to wiring called subtractive aluminum, blanket films of aluminum are deposited, patterned and etched to form the wires. A dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes, called vias, in the insulating material and depositing tungsten in the holes. This approach is still used in the fabrication of memory chips such as DRAMs as the number of interconnect levels is small.
More recently, as the number of interconnect levels has increased due to the large number of transistors that now need to be interconnected in a modern microprocessor, the timing delay in the wiring has become significant, prompting a change in wiring material from aluminum to copper and from the silicon dioxides to newer low-K material. The result is not only enhanced performance but reduced cost as well in that damascene processing is substituted for subtractive aluminum technology, thereby elimination several steps. In damascene processing, the dielectric material is deposited as a blanket film, which is then patterned and etched leaving holes or trenches. In single damascene processing, copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting in filled vias or wire lines. In dual damascene technology, both the trench and via are fabricated before the deposition of copper resulting in formation of both vias and wire lines simultaneously, further reducing the number of processing steps. The thin barrier film, called copper barrier seed (CBS), is necessary to prevent copper diffusion into the dielectric. The ideal barrier film is as thin as possible. As the presence of excessive barrier film competes with the available copper wire cross section, formation of the thinnest continuous barrier represents one of the greatest ongoing challenges in copper processing today.
As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked and extend outside the depth of focus of available lithography, interfering with the ability to pattern. CMP (chemical mechanical planarization) is a processing method to achieve such planarization although dry etch back is still sometimes employed if the number of interconnect levels is low.
The above process, although described specifically with regard to silicon chip manufacture, is fairly generic for most types of printed circuits, printed circuit boards, antennas, solar cells, solar thin films, semiconductors and the like. As can be seen, the process is subtractive; that is a metal, usually copper, is deposited uniformly over a substrate surface and then unwanted metal, that is, metal that does not comprise some part of the final circuit, is removed. A number of additive processes are known, which resolve some of the problems associated with the subtractive process but which engender problems of their own, a significant one of which involves adherence of a built-up conducting layer to the substrate.
What is needed is an additive process for integrated circuit fabrication that has all of the advantages of other additive processes but which exhibits improved adhesion properties to substrates. The current invention provides such an additive process.